? semiconductor components industries, llc, 2003 august, 2003 ? rev. 3 publication order number: umz1nt1/d umz1nt1 complementary dual general purpose amplifier transistor pnp and npn surface mount ? high voltage and high current: v ceo = 50 v, i c = 200 ma ? high h fe : h fe = 200 400 ? moisture sensitivity level: 1 ? esd rating ? human body model: 3a esd rating ? machine model: c maximum ratings (t a = 25 c) rating symbol value unit collector?base voltage v (br)cbo 60 vdc collector?emitter voltage v (br)ceo 50 vdc emitter?base voltage v (br)ebo 7.0 vdc collector current ? continuous i c 200 madc thermal characteristics characteristic (one junction heated) symbol max unit total device dissipation t a = 25 c derate above 25 c p d 187 (note 1) 256 (note 2) 1.5 (note 1) 2.0 (note 2) mw mw/ c thermal resistance ? junction-to-ambient r ja 670 (note 1) 490 (note 2) c/w characteristic (both junctions heated) symbol max unit total device dissipation t a = 25 c derate above 25 c p d 250 (note 1) 385 (note 2) 2.0 (note 1) 3.0 (note 2) mw mw/ c thermal resistance ? junction-to-ambient r ja 493 (note 1) 325 (note 2) c/w thermal resistance ? junction-to-lead r jl 188 (note 1) 208 (note 2) c/w junction and storage temperature t j , t stg ?55 to +150 c 1. fr?4 @ minimum pad 2. fr?4 @ 1.0 x 1.0 inch pad http://onsemi.com sc?88 case 419b marking diagram 1 2 3 3z m 3z = specific device code m = date code device 2 package shipping ordering information umz1nt1 sc?88 3000/tape & reel 2the at1o suffix refers to a 7 inch reel. q 1 (4) (5) (6) (1) (2) (3) q 2 6 5 4
umz1nt1 http://onsemi.com 2 q1: npn electrical characteristics (t a = 25 c unless otherwise noted) characteristic symbol min typ max unit collector?emitter breakdown voltage (i c = 2.0 madc, i b = 0) v (br)ceo 50 ? ? vdc collector?base breakdown voltage (i c = 10 adc, i e = 0) v (br)cbo 60 ? ? vdc emitter?base breakdown voltage (i e = 10 adc, i c = 0) v (br)ebo 7.0 ? ? vdc collector?base cutoff current (v cb = 45 vdc, i e = 0) i cbo ? ? 0.1 adc collector?emitter cutoff current (v ce = 10 vdc, i b = 0) (v ce = 30 vdc, i b = 0) (v ce = 30 vdc, i b = 0, t a = 80 c) i ceo ? ? ? ? ? ? 0.1 2.0 1.0 adc adc madc dc current gain (note 3) (v ce = 6.0 vdc, i c = 2.0 madc) h fe 200 ? 400 ? collector?emitter saturation voltage (i c = 100 madc, i b = 10 madc) v ce(sat) 0.15 ? 0.25 vdc transistor frequency f t ? 114 ? mhz 3. pulse test: pulse width 300 s, d.c. 2%. q2: pnp electrical characteristics (t a = 25 c unless otherwise noted) characteristic symbol min typ max unit collector?emitter breakdown voltage (i c = 2.0 madc, i b = 0) v (br)ceo ?50 ? ? vdc collector?base breakdown voltage (i c = 10 adc, i e = 0) v (br)cbo ?60 ? ? vdc emitter?base breakdown voltage (i e = 10 adc, i c = 0) v (br)ebo ?7.0 ? ? vdc collector?base cutoff current (v cb = 45 vdc, i e = 0) i cbo ? ? ?0.1 adc collector?emitter cutoff current (v ce = 10 vdc, i b = 0) (v ce = 30 vdc, i b = 0) (v ce = 30 vdc, i b = 0, t a = 80 c) i ceo ? ? ? ? ? ? ?0.1 ?2.0 ?1.0 adc adc madc dc current gain (note 3) (v ce = 6.0 vdc, i c = 2.0 madc) h fe ?200 ? ?400 ? collector?emitter saturation voltage (i c = 100 madc, i b = 10 madc) v ce(sat) ?0.15 ? ?0.3 vdc transistor frequency f t ? 142 ? mhz
umz1nt1 http://onsemi.com 3 typical electrical characteristics: pnp transistor figure 1. collector saturation region 0?1?2?3?4 ?6 ?5 ?200 0 ?40 i c , collector current (ma) v ce , collector?emitter voltage (v) ?80 ?120 ?160 figure 2. dc current gain ?1 ?10 ?100 ?1000 1000 10 h fe , dc current gain i c , collector current (ma) 100 t a = 25 c ?2.0 ma ?1.5 ma ?1.0 ma ?0.5 ma i b = ?0.2 ma v ce = ?1.0 v t a = 100 c ?25 c 25 c figure 3. dc current gain ?1 ?10 ?1000 ?100 1000 10 h fe , dc current gain i c , collector current (ma) 100 figure 4. v ce(sat) versus i c ?1 ?10 ?100 ?1000 ?1 ?0.01 v ce(sat) , maximum collector voltage (v) i c , collector current (ma) ?0.1 i c /i b = 10 t a = 100 c ?25 c 25 c t a = 100 c ?25 c 25 c figure 5. v be ( sat ) versus i c ?1 ?10 ?1000 ?100 ?10 ?0.1 base?emitter saturation voltage (v) i c , collector current (ma) ?1 figure 6. base?emitter voltage 0 ?0.1 ?10,000 i b , base current ( a) v be , base?emitter voltage (v) ?0.1 common emitter v ce = 6 v t a = 100 c ?25 c 25 c t a = 25 c i c /i b = 10 ?1 ?10 ?100 ?1000 ?0.2 ?0.3 ?0.4 ?0.5 ?0.6 ?0.7 ?0.8 ?0.9 ?1 v ce = ?6.0 v
umz1nt1 http://onsemi.com 4 typical electrical characteristics: npn transistor figure 7. collector saturation voltage 01 2 3 4 6 5 280 0 40 i c , collector current (ma) v ce , collector?emitter voltage (v) 80 120 160 figure 8. dc current gain 1 10 100 1000 1000 10 h fe , dc current gain i c , collector current (ma) 100 t a = 25 c 6.0 ma 1.0 ma i b = 0.2 ma v ce = 1.0 v t a = 100 c ?25 c 25 c figure 9. dc current gain 1 10 1000 100 1000 10 h fe , dc current gain i c , collector current (ma) 100 figure 10. v ce(sat) versus i c 1 10 100 1000 1 0.01 v ce(sat) , maximum collector voltage (v) i c , collector current (ma) 0.1 i c /i b = 10 t a = 100 c ?25 c 25 c t a = 100 c ?25 c 25 c figure 11. v be ( sat ) versus i c 1 10 1000 100 10 0.1 base?emitter saturation voltage (v) i c , collector current (ma) 1 figure 12. base?emitter voltage 0 0.1 10,000 i b , base current ( a) v be , base?emitter voltage (v) 0.1 common emitter v ce = 6 v t a = 100 c ?25 c 25 c t a = 25 c i c /i b = 10 1 10 100 1000 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 5.0 ma 3.0 ma 200 240 2.0 ma 0.5 ma v ce = 6.0 v
umz1nt1 http://onsemi.com 5 0.5 mm (min) 0.4 mm (min) 0.65 mm 0.65 mm 1.9 mm the values for the equation are found in the maximum ratings table on the data sheet. substituting these values into the equation for an ambient temperature t a of 25 c, one can calculate the power dissipation of the device which in this case is 150 milliwatts. information for using the sc?88 surface mount package minimum recommended footprint for surface mounted applications surface mount board layout is a critical portion of the to- tal design. the footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. with the cor- rect pad geometry, the packages will self align when sub- jected to a solder reflow process. sc?88 power dissipation p d = t j(max) ? t a r q ja p d = 150 c ? 25 c 833 c/w = 150 milliwatts the power dissipation of the sc?88 is a function of the pad size. this can vary from the minimum pad size for sol- dering to a pad size given for maximum power dissipation. power dissipation for a surface mount device is determined by t j(max) , the maximum rated junction temperature of the die, r q ja , the thermal resistance from the device junction to ambient, and the operating temperature, t a . using the values provided on the data sheet for the sc?88 package, p d can be calculated as follows: the 833 c/w for the sc?88 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 150 milliwatts. there are other alternatives to achieving higher power dis- sipation from the sc?88 package. another alternative would be to use a ceramic substrate or an aluminum core board such as thermal clad ? . using a board material such as thermal clad, an aluminum core board, the power dis- sipation can be doubled using the same footprint. soldering precautions the melting temperature of solder is higher than the rated temperature of the device. when the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. there- fore, the following items should always be observed in or- der to minimize the thermal stress to which the devices are subjected. ? always preheat the device. ? the delta temperature between the preheat and solder- ing should be 100 c or less.* ? when preheating and soldering, the temperature of the leads and the case must not exceed the maximum tem- perature ratings as shown on the data sheet. when using infrared heating with the reflow soldering meth- od, the difference shall be a maximum of 10 c. ? the soldering temperature and time shall not exceed 260 c for more than 10 seconds. ? when shifting from preheating to soldering, the maxi- mum temperature gradient shall be 5 c or less. ? after soldering has been completed, the device should be allowed to cool naturally for at least three minutes. gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. ? mechanical stress or shock should not be applied dur- ing cooling. * soldering a device without preheating can cause exces- sive thermal shock and stress which can result in damage to the device sc?88
umz1nt1 http://onsemi.com 6 step 1 preheat zone 1 ramp" step 2 vent soak" step 3 heating zones 2 & 5 ramp" step 4 heating zones 3 & 6 soak" step 5 heating zones 4 & 7 spike" step 6 vent step 7 cooling 200 c 150 c 100 c 50 c time (3 to 7 minutes total) t max solder is liquid for 40 to 80 seconds (depending on mass of assembly) 205 to 219 c peak at solder joint desired curve for low mass assemblies 100 c 150 c 160 c 140 c figure 13. typical solder heating profile desired curve for high mass assemblies 170 c for any given circuit board, there will be a group of con- trol settings that will give the desired heat pattern. the op- erator must set temperatures for several heating zones, and a figure for belt speed. taken together, these control set- tings make up a heating aprofileo for that particular circuit board. on machines controlled by a computer, the comput- er remembers these profiles from one operating session to the next. figure 7 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. this profile will vary among soldering systems but it is a good starting point. factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. this pro- file shows temperature versus time. solder stencil guidelines prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. a solder stencil is required to screen the optimum amount of solder paste onto the footprint. the stencil is made of brass or stainless steel with a typical thickness of 0.008 inches. the stencil opening size for the surface mounted package should be the same as the pad size on the printed circuit board, i.e., a 1:1 registration. typical solder heating profile the line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. the two profiles are based on a high density and a low density board. the vitronics smd310 convection/infrared reflow soldering system was used to generate this profile. the type of solder used was 62/36/2 tin lead silver with a melting point between 177?189 c. when this type of furnace is used for solder re- flow work, the circuit boards and solder joints tend to heat first. the components on the board are then heated by con- duction. the circuit board, because it has a large surface area, absorbs the thermal energy more ef ficiently, then dis- tributes this energy to the components. because of this ef- fect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.
umz1nt1 http://onsemi.com 7 package dimensions sc?88 case 419b?02 issue n notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. 419b?01 obsolete, new standard 419b?02. dim a min max min max millimeters 1.80 2.20 0.071 0.087 inches b 1.15 1.35 0.045 0.053 c 0.80 1.10 0.031 0.043 d 0.10 0.30 0.004 0.012 g 0.65 bsc 0.026 bsc h ??? 0.10 ??? 0.004 j 0.10 0.25 0.004 0.010 k 0.10 0.30 0.004 0.012 n 0.20 ref 0.008 ref s 2.00 2.20 0.079 0.087 b 0.2 (0.008) mm 123 a g s h c n j k 654 ?b? d 6 pl
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